In recent years, variable resistance nonvolatile memory devices (hereinafter, referred to also simply as “nonvolatile memory devices”) having memory cells including variable resistance nonvolatile memory elements (hereinafter, referred to also simply as “variable resistance elements”) have been researched and developed. The variable resistance elements are elements having characteristics in which a resistance value reversibly changes based on electrical signals, and capable of holding data corresponding to the resistance value in a nonvolatile manner.
Commonly known is a nonvolatile memory device including a matrix of so-called 1T1R memory cells in each of which a Metal Oxide Semiconductor (MOS) transistor and a variable resistance element are connected in series with each other at a location close to a cross-point between a bit line and a word line that are arranged perpendicular to each other. In each of the 1T1R memory cells, one of two terminals of the variable resistance element is connected to the bit line or a source line, while the other terminal is connected to a drain or source of the MOS transistor. A gate of the MOS transistor is connected to the word line. The other terminal of the MOS transistor is connected to the source line or the bit line which is not connected to the terminal of the variable resistance element. The source line is arranged parallel to the bit line or the word line.
Another memory cell structure is also generally known as a nonvolatile memory device including a matrix of cross point memory cells called 1D1R memory cells in each of which a diode and a variable resistance element are connected in series with each other at a cross-point between a bit line and a word line that are arranged perpendicular to each other.
(Definition of Forming)
The following describes typical examples of conventional variable resistance elements (Non-Patent Literature 1, and Patent Literatures 1 and 2).
First, Non-Patent Literature 1 discloses the following nonvolatile memory including 1T1R memory cells each using a transition metal oxide as a variable resistance element. A transition metal oxide thin film is generally a super high resistance that is almost an insulator before forming, and its resistance is not changed even by applying a voltage having a pulse voltage (hereinafter, expressed also as “applying a pulse voltage”). A resistance value of the transition metal oxide film can therefore be changed by application of a voltage pulse, by performing a forming to form a conducting path for switching the resistance value between a high resistance state and a low resistance state. Here, the forming (or forming processing) refers to initialization processing of a variable resistance element. The forming is an operation for changing a variable resistance element from a state having an extremely high resistance value after manufacture of the variable resistance element (in other words, an initial state where a voltage has not yet been applied after manufacturing) to an operable state where a resistance value of the variable resistance element is in a range lower than the initial state and can be changed between a high resistance state and a low resistance state according to application of a pulse voltage. In other words, the forming is used to change the variable resistance element from a state after the manufacture where the variable resistance element has not yet operated as a variable resistance element to a state where the variable resistance element is capable of serving as a variable resistance element. In general, the forming is performed only once after the manufacture.
(Disclosures Regarding Forming of Variable Resistance Element in Patent Literature 1 and Non-Patent Literature 1)
FIG. 35 is a graph plotting a dependency of a forming voltage (V_form) on a transition metal oxide film thickness (TMO) which is disclosed in Non-Patent Literature 1. The “forming voltage” refers to a voltage applied to perform a forming for a variable resistance element. The graph indicates four kinds of properties, NiO, TiO2, HfO2, and ZrO2, as transition metal oxides. The forming voltage depends on the kinds of the transition metal oxides. Furthermore, when a thickness of a transition metal oxide is greater, the forming start voltage is higher. It is disclosed that, in order to decrease the forming voltage, it is therefore preferable to select a transition metal oxide such as NiO to form a transition metal oxide film having a small thickness.
Moreover, Patent Literature 1 discloses a metal ion conductive nonvolatile memory element in which rare earth oxide thin films are used as variable resistance elements.
FIG. 36 is a cross-sectional view of a memory cell disclosed in Patent Literature 1.
This memory cell has the following structure. A lower electrode 2 is formed on a substrate 1 having a high electrical conductivity (a silicon substrate 1 doped with a P-type high-concentration impurity, for example). An ion source layer 3 including a metallic element as an ion source is formed on the lower electrode 2. A memory layer 4 having a relatively high resistance value is formed on the ion source layer 3. An upper electrode 6 is formed to contact the memory layer 4 through an opening in an insulation layer 5 on the memory layer 4.
Patent Literature 1 discloses CuTe, GeSbTe, AgGeTe, and the like as a material of the ion source layer 3, and discloses a rear earth element oxide such as a gadolinium oxide as a material of the memory layer 4. A material of the lower electrode 2 and the upper electrode 6 is described as a common semiconductor line material such as TiW and TaN. Furthermore, a gadolinium oxide for the memory layer 4 is added with metallic particles such as Cu having an amount not enough to form a layer, namely, an amount enough to keep insulation properties or semi-insulation properties.
A method of writing data into the memory cell shown in FIG. 36 is as follows. When a negative voltage causing a potential of the upper electrode 6 to be lower than a potential of the lower electrode 2, a conducting path including a large amount of metallic elements is formed in the memory layer 4, or a large number of defects resulting from the metallic elements are formed in the memory layer 4. As a result, a resistance value of the memory layer 4 is decreased. On the other hand, when a positive voltage causing the potential of the upper electrode 6 to be higher than the potential of the lower electrode 2 is applied, the conducting path or the defects formed in the memory layer 4 due to the metallic elements disappear. As a result, the resistance value of the memory layer 4 is increased.
FIG. 37 is a graph plotting I-V properties changed from an initial state regarding the memory cell shown in FIG. 36. In the first loop, a relatively high negative voltage is applied to the memory cell to change a high resistance state of the initial state to a low resistance state. The voltage is assumed to be an initialization voltage Vo. Then, when a positive potential is increased, an erasing voltage Ve is applied to the memory cell to change the low resistance state to a high resistance state. Furthermore, after the first loop, a writing voltage Vr having an absolute value smaller than that of the initialization voltage Vo is applied to the memory cell to change the high resistance state to a low resistance state.
As described above, according to Patent Literature 1, once initialization is first performed by the high voltage Vo, the resistance state can be afterwards changed by the low erasing voltage Ve and writing voltage Vr. Patent Literature 1 also discloses that the initialization voltage Vo can be controlled by adding metal particles to the memory layer 4 to form defection caused by the metal element in the memory layer 4.
(Disclosure Regarding Forming of Variable Resistance Element in Patent Literature 2)
Furthermore, Patent Literature 2 disclose an initialization (forming) method for ion conductive nonvolatile variable resistance elements, by which data writing and erasing after initialization can be performed at a high speed.
FIG. 38 shows an initial pulse waveform for performing the initialization which is disclosed in Patent Literature 2. As shown in FIG. 38, without performing initialization by a pair of a writing voltage pulse and an erasing voltage pulse, writing and erasing are repeated alternately so that a pulse width is gradually decreased from a long pulse of approximately a few hundred ms which is a required minimum pulse for initialization to a desired pulse width for data writing and erasing.
More specifically, the first pair of a writing voltage pulse PW1 and an erasing voltage pulse PE1 is set to be a long pulse having a width o approximately a few hundred ms. The second pair of a writing voltage pulse PW2 and an erasing voltage pulse PE2 is set to have a pulse width slightly shorter than the pulse width of the first pair of the pulse PW1 and the PE1. The third pair of a writing voltage pulse PW3 and an erasing voltage pulse PE3 is set to have a further shorter pulse width. Then, the fourth pair of a writing voltage pulse PW4 and an erasing voltage pulse PE4 is set to have the same pulse width as a pulse width of voltage pulses for subsequent data writing and erasing.
Therefore, Patent Literature 2 discloses that, by performing initialization (forming) to change a pulse width from a long pulse width to a short pulse width after application of voltage having the long pulse width, it is possible to perform data writing and erasing at a high speed with the short pulse width.